FPGA Implementation Lead

At Ludwig Computing, we are solving the energy efficiency problem of intelligent compute. Our novel co-designed approach is optimized to deliver radical improvements in energy efficiency and performance across a wide range of compute-intensive workloads. Join us at the ground floor as we build the future of intelligent compute. We are hiring an experienced FPGA / RTL implementation lead to help drive the development of Ludwig’s first hardware acceleration platform. You will translate a broader hardware architecture into a staged FPGA implementation plan — concrete module boundaries, interfaces, validation milestones, bring-up steps, and realistic development timelines — while mentoring junior engineers. Responsibilities Lead the FPGA implementation plan for Ludwig’s first hardware acceleration prototype, from architecture decomposition through block-level validation and system bring-up. Translate high-level hardware architecture into concrete module boundaries, interfaces, test plans, ownership assignments, and development milestones. Review and guide RTL development across datapaths, control logic, memory interfaces, and host/FPGA communication paths, contributing directly to critical or blocking pieces when needed. Guide FPGA bring-up and integration on modern FPGA platforms and development flows. Establish strong verification practices, including golden-model comparison, deterministic unit tests, simulation infrastructure, and clear definitions of done for each block. Analyze resource utilization, timing, memory bandwidth, and throughput bottlenecks to guide architecture and implementation decisions. Requirements Significant experience with FPGA and/or ASIC RTL development using Verilog or SystemVerilog, ideally including prior ownership of a nontrivial subsystem or prototype. Strong understanding of digital design, pipelined datapaths, finite-state machines, memory systems, clocking/reset, timing closure, and hardware verification. Experience bringing up nontrivial designs on FPGA platforms using Vivado or comparable FPGA toolchains. Familiarity with AXI, AXI-Lite, AXI-MM, DMA-based data movement, host/FPGA interfaces, and memory-mapped control. Ability to decompose complex hardware systems into clean module boundaries, interfaces, verification plans, and implementation milestones. #J-18808-Ljbffr