DFX Verification Engineer

Role: DFX Verification EngineerLocation: Bay Area, CA, Santa Clara, CA (Onsite)Experience: 4+ yearsKey ResponsibilitiesDevelop and execute verification plans for DFx features including:Scan (stuck-at, transition fault)MBIST / LBISTBoundary Scan (JTAG)Memory repair and redundancyLow-power test scenariosCreate and maintain testbenches using SystemVerilog/UVM for DFx validationVerify:Scan chain integrity and connectivityTest mode functionality and coverageATPG pattern validation and debugBIST controllers and memory test logicTechnical SkillsStrong knowledge of:DFT concepts (Scan, ATPG, MBIST, JTAG)Digital design fundamentalsExpertise in:SystemVerilog and UVMSimulation tools (VCS, Xcelium, Questa)Familiarity with:ATPG tools (TetraMAX, Modus, FastScan)Debug tools (Verdi, DVE)Understanding of:Low-power design (UPF/CPF)Clocking and reset strategies