RTL Design Engineer

Responsibilities:Develop RTL for processor datapath componentsDesign blocks such as:ALULoad/Store unitsVector / Matrix execution unitsRegister filesInstruction decode / execution pipelinesImplement microarchitecture in Verilog/SystemVerilogWork closely with verification teams to ensure design correctnessSupport front-end design flows (lint, CDC, synthesis)Requirements:5+ years RTL design experienceStrong Verilog / SystemVerilogExperience with CPU datapath designFamiliarity with vector or matrix compute unitsPreferred:RISC-V architecture knowledgeExperience in processor pipeline design