Remote Senior ASIC Verification Engineer-SystemVerilog/UVM

A leading semiconductor company is seeking a Sr Design Verification Engineer to verify complex digital systems, including ARM-based CPUs and DSP blocks. The ideal candidate has over 10 years of ASIC verification experience, strong proficiency in SystemVerilog and UVM, and has solid scripting skills in Python. This position offers an anticipated annual salary between $150,000 to $165,000, comprehensive benefits, and the opportunity to work remotely. #J-18808-Ljbffr