Design Automation Intern

Company DescriptionJoin a multibillion-dollar global company that brings together amazing technology, people, and operational scale to become a powerhouse in the memory industry. Headquartered in Rancho Cordova, California, Solidigm combines elements of an established, successful technology company with the spirit, agility, and entrepreneurial mindset of a start-up. In addition to the U.S. headquarters and other facilities in the U.S., the company has international presence in Asia, Europe, and the Americas. Solidigm will continue to lead the world in innovating new Memory technologies with aspirations to be the #1 NAND memory company in the world. At Solidigm, we view problems as opportunities to define innovative solutions that hold the power to change the world and unleash the potential technological needs that the future holds. At Solidigm, we are One Team that fosters a diverse, equitable, and inclusive culture that embraces individual uniqueness and empowers us to bring our best selves to deliver excellence in support of Solidigm's vision and mission to be the go-to partner for optimized data storage solutions. You can be part of the takeoff of an innovative business that develops cutting-edge products, delivers strong business value for customers, provides an engaging workplace for its employees, and serves a greater impact on the world. This is a golden opportunity for the right applicant to join us and help design, build, and lead Solidigm. We want a diverse team of dedicated professionals who will not just be Solidigm team members but contribute to how we shape the future of the organization. We are seeking applicants who will grow and thrive in our culture; be customer inspired, trusting, innovative, team-oriented, inclusive, results driven, collaborative, passionate, and flexible.Job DescriptionWe are seeking a Design Automation Intern to support and enhance Quality Assurance (QA) for custom design automation flows. This role will focus on expanding QA coverage for P‑Cells, runsets, and design project environments, with a strong emphasis on leveraging AI techniques to improve validation depth, scalability, and defect detection. The intern will work closely with senior Design Automation engineers on production‑critical flows that directly impact design correctness, productivity, and risk reduction across multiple technology nodes.Key Responsibilities1. P‑Cell & Runset QA AutomationDevelop and execute QA workflows for P‑Cells to validate parameter coverage, geometry correctness, and rule complianceAssist with runset verification QA (e.g., DRC/LVS regressions), ensuring consistent results across environments and tool versionsImprove regression coverage and identify gaps in existing manual and automated QA checks2. AI‑Assisted QA Coverage ExpansionApply AI/ML or data‑driven techniques to:Detect anomalies in QA results and regression outputsIdentify under‑tested parameter spaces or design conditionsPropose intelligent test selection to maximize QA coverage with minimal runtimePrototype scripts or tools that integrate AI‑assisted analysis into existing DA QA flows3. Project Environment & Infrastructure QACreate QA checks to validate design project environments, including:Project setup correctness (databases, directory structures, permissions)Consistency of design databases and metadataBasic validation of selected EDA tools within the project environmentHelp define pass/fail criteria and reporting for environment readiness checks4. Documentation & HandoffDocument QA methodologies, scripts, and resultsCreate clear summaries and dashboards to communicate QA findings to DA and design teamsQualificationsPursuing a BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related fieldFamiliarity with EDA concepts (layout, verification, PDKs, runsets, or physical design flows)Programming or scripting experience in Python, SKILL, TCL, or similar languagesStrong analytical skills and interest in automation and quality engineeringProblem solving skills are very importantPreferred QualificationsExposure to physical verification (DRC/LVS/XOR) or P‑Cell developmentExperience with AI/ML, data analysis, or anomaly detection (coursework or projects)Familiarity with Linux environments and version control (e.g., Git)Interest in semiconductor design infrastructure and automation