Remote RTL Design Engineer for AI-Enabled ASICs

Mercor is hiring RTL Design Engineers to evaluate and enhance AI model training for digital chip design and verification. This remote role offers a competitive hourly compensation ranging from $100 to $175, with a commitment of 40 hours/week for at least 3 months. Candidates must have 3 to 10 years of experience in digital RTL design or verification, with strong skills in Verilog/SystemVerilog and an understanding of ASIC design flows. The start date is the week of April 23. J-18808-Ljbffr