Memory Design Engineer

Memory Design EngineerMilpitas CAJob Description:We are looking for a high-caliber engineer with rich PCle experience to own the end-to-end system design for our next-generation NVMe SSD product lines. You will bridge the gap between ASIC/SoC integration, firmware architecture, and platform interoperability.Core Responsibilities• Architecture & Design: Own the system-level PCle Gen5/ Gen6 architecture from an endpoint perspective, including PHY/MACreview and SoC integration.• Driver & FirmwareLeadership: Serve as a technical lead for high-performance PCle kernel-mode drivers (Linux/Windows) and define firmware guidelines for robust link training (LTSSM) and power management.• Complex Topologies:Architect driver logic for sophisticated hardwaresetups involving external PCle switches and multiple endpoints.• Validation & Debug: Lead system-level triage for PCle behaviors, including AER (Advanced Error Reporting), reset flows, and interoperability across diverse host platforms.• Compliance: Ensure full adherence to PCI-SIG standards and NVMe specifications during bring-up and qualification.• Mentorship: Providetechnical direction and mentor junior engineers, fostering a culture of excellence in low-level software and high-speed design.Required Skills & Qualifications• Protocol Expertise: Deep knowledge of PCle Gen5/ Gen6, NVMe, and high-speed interface solutions like SerDes.• Programming: Proficient in C/ C++ for embedded systems and Python for test automation and triage.• Lab Proficiency: Hands-on experience with protocol analyzers, oscilloscopes, and logic analyzers for hardware/ firmware debug.• Architecture: Strong understanding of SoC/ASIC registers, power domains, and sideband signaling.