RTL Design Engineer, Machine Learning Accelerators

Overview In this role you design and improve ASIC blocks to support AI/ML workloads, collaborating with software teams to ensure robust interfaces and timing. You contribute to TPU architecture and its integration into AI systems, shaping future silicon for a hyperscale environment. You’ll verify complex digital designs and apply high-performance, low-power concepts. This is a mission-driven role within Google’s AI and Infrastructure team, offering unique impact at scale. Compensation / Benefitsbonus targetequitybenefits ResponsibilitiesDesign and document ASIC blocks with functionality and timingVerify complex digital designs focusing on TPU architectureCollaborate with software teams on interfaces and documentationShape TPU hardware integration and performance in AI/ML workloadsApply engineering best practices in design and verificationContribute to scalable, energy-efficient accelerator development Key requirementsBachelor's degree in electrical engineering, computer engineering, computer science, or related field; or equivalent practical experience4 years of experience with custom silicon design (e.g., SoCs, ASICs)Experience with RTL design using Verilog or SystemVerilogExperience interacting with software, architecture, and cross-functional teamsStrong communication and documentation skillsability to work in fast-paced, high-impact environmentsRTL design with Verilog/SystemVerilogCustom silicon design (SoCs/ASICs)Knowledge of TPU architecture and AI/ML hardware acceleration