Formal Verification Engineer

Role Overview This position requires a specialized Verification Engineer who is adept at using tools like Jasper C2RTL or SLEC tools for formal verification. The focus is on verifying arithmetic components in integrated circuits The Verification Engineer will focus on verifying the functionality and accuracy of integrated circuits, particularly in the arithmetic data path. This involves using specialized tools to ensure the design's logical equivalence and accuracy in complex digital systems. Key Requirements Primary Skills (Ideal Candidate): Hands-on experience with Jasper C2RTL: Experience in using the JasperGold C2RTL (Control-to-RTL) verification platform, a Cadence tool for formal verification that helps check if the RTL code matches high-level design specifications. Location: Based in Austin, TX, or Santa Clara, CA. Alternative Skills (Otherwise): Experience with Sequential Logical Equivalence Checking (SLEC): Familiarity with SLEC tools, which are used to verify the equivalence between different design representations over time (sequential verification). Experience with other tools like HECTOR from Synopsys, a tool similar to Jasper for performing formal verification and equivalence checking. US-based candidates who are open to visiting Austin for onboarding or to facilitate the ramp-up process. Additional Skills: Arithmetic Data Path Verification: Proficiency in verifying complex arithmetic operations, ensuring the accuracy and performance of components like multipliers, adders, ALUs (Arithmetic Logic Units), etc. Job Type: Contract Schedule: 8 hour shift Experience: Jasper C2RTL: 3 years (Preferred) Sequential Logical Equivalence Checking (SLEC): 3 years (Preferred) HECTOR from Synopsys or equivalent formal verification tools: 3 years (Preferred) Arithmetic Data Path Verification: 3 years (Preferred) analyze, verify, and validate RTL code: 3 years (Preferred) Python, Perl, or Tcl to manage verification environments: 3 years (Preferred) ModelSim, VCS, or Questa: 3 years (Preferred) UVM (Universal Verification Methodology) or SystemVerilog: 2 years (Preferred) Ability to Commute: Austin, TX 78744 (Required) Ability to Relocate: Austin, TX 78744: Relocate before starting work (Required) Work Location: In person