RTL (DSP) Engineer

We are looking for a qualified and highly motivated candidate for the development of signal processing RTL blocks and subsequent implementations. This will be a hands-on position, designing/implementing critical DSP blocks. *Requirements* * MS or PhD degree emphasis in ASIC and DSP design * Five or more years of experience in RTL design using Verilog and System Verilog * Experience in developing & optimizing DSP related RTL blocks and test and verification of DSP blocks * Previous exposure to physical layer of communication chips such as Wi-Fi, BLE, GNSS, or cellular is a plus * Design of state machines, data paths, arbitration, and clock domain crossing logic * Logic synthesis support, FPGA implementation, Timing constraints * Exposure to Design for Test, understanding of scan concept and writing DFT friendly RTL * Unified Power Format for simulation, synthesis, and electrical rule checking Equivalence checking * Accurate power estimation for RTL blocks * Committed to producing high-quality design * Team player and excellent interpersonal, communication and writing skills Job Type: Full-time Pay: $83,942.09 - $172,576.12 per year Schedule: * 8 hour shift Work Location: In person