ASIC RTL/SoC Design Engineer

Responsibilities:Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designsIntegrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibilityThoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offsCollaborate closely with the backend team, participating in RTL coding, implementation, and synthesis stages to ensure successful tapeoutDevelop and maintain reusable internal intellectual properties (IPs) tailored for AI and/or in-memory computing applicationsProvide crucial support for Post-Si testing and validation, diagnosing and rectifying issues to ensure the overall functionality and quality of the productPlay a mentorship role by guiding and coaching junior engineers, sharing expertise and best practices to foster their professional growthContribute to design reviews and cross-functional discussions, offering insights and recommendations to enhance product performance and reliabilityStay up-to-date with industry trends and advancements in RTL design methodologies, integrating innovative techniques to improve product quality and efficiencyCollaborate with cross-functional teams, including software, architecture, and verification teams, to achieve cohesive and successful product development and deliveryRequirements:MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital designExperience with Verilog and system VerilogExperience with VCS, Verdi or other industry standard toolsExperience with pre-layout simulation and post-layout simulationUnderstanding of the design flow. Ability to work with the backend teamFamiliarity with AMBA APB AXI ProtocolFamiliarity with RISC/Arm or other core architecturesAbility to create innovative architecture and solutions to customer requirementsAbility to work in startup environment and work both independently and as a team player, with the ability to provide technical leadership to other members of the engineering team.Experience in one or more of the following areas considered a strong plus:FPGA/ASIC design of image processing systemsWorking knowledge of SoC architecture such as CPU, GPU or acceleratorsFamiliarity with: UVM, place-and-route, STA, EM/IR/Power