DFT Application Engineer

Overview As a DFT Application Engineer at Intel Foundry Services, you will deliver DFT/DFM solutions and support to ADG customers to enable successful tape-outs. You will work with cross-functional teams to resolve complex issues and drive quality improvements across block- and SoC-level implementations. You will develop technical content and training to empower customers and internal teams, shaping robust DFT flows for advanced CMOS processes. This role offers high-impact engagement in aerospace, defense, and government projects and the chance to influence critical semiconductor design quality. Compensation / Benefitscutting-edge DFT technologiesdirect customer engagementaccess to advanced foundry technologies and EDA tool suitescompetitive compensationprofessional development in DFT methodologiesimpact on national security through advanced semiconductor solutions ResponsibilitiesProvide end-to-end DFT tool/flow/methodology support to resolve customer issues and enable successful tape-outsCollaborate with internal teams, foundry customers, IP providers, and EDA vendors to address complex technical challengesDeliver customer-facing guidance on DFT implementation strategiesLead quality improvements in ASIC DFT/DFM and ATPG validation methodology for block-level and SoC-level designsCoordinate with RTL and Hard IP designers on DFT/DFM methodology and with physical designers on DFT/DFM physical implementation, validation, and timing signoffDevelop and optimize DFT insertion flows for advanced CMOS processes and multi-die designsCreate application notes, documentation, and deliver technical training to customers and internal teamsCreate best practice guidelines for DFT implementation across varying design complexitiesSupport knowledge transfer and capability building for internal teams and customers Key requirementsUS citizenshipAbility to obtain US Government Security ClearanceBachelor's degree in Electrical Engineering, Computer Engineering, or STEM-related field3+ years of experience with advanced CMOS processes (22nm and below)3+ years of experience implementing ASIC DFT/DFM insertion (MBIST, LBIST, SCAN, JTAG) at block and full-chip level with ATPG validation and DFT timing/signoff at SOC level2+ years of scripting experience (Python, Perl, Tcl, or shell)Proven customer-facing experience and ability to manage multiple complex tasksCustomer-focused mindsetSelf-motivated and results-orientedCollaborative team playerDFT/DFM insertion and ATPG validationMBIST/LBIST/SCAN/JTAG techniquesATPG timing/signoff at SOC level