Design Verification Engineer

Design Verification EngineerLocation: Bay Area (Day1 onsite preferable)Client: Google, Facebook, Cisco, Intel Mandatory: UVM minimum 3 years of experience also share a write up along with the submissionMust be proficient with:Building a test bench for a block using System Verilog and UVMWriting random tests, directed tests, error tests & performance tests for a block of Verilog and UVM.Developing, maintaining and supporting of the UVM verification environment.Debugging tests with design engineers to deliver functionally correct design blocksWriting & analyzing functional coverage, assertionsGenerating and analyzing code coverage & writing waivers.Thanks & Regards,Akhil Reddy VontelaSoftware Technology Inc100 Overlook Center, Suite 200 Princeton, NJ 08540.Email: Akhil.reddy@stiorg.comContact: 6096697444