Physical Design Engineer

Eximietas Design is hiring a Lead Physical Design (PNR) Engineer to drive high-quality implementation for advanced-node SoCs, including AI and multi-die designs. This role is hands-on and focused on delivering robust, signoff-clean physical design.Location: San Francisco Bay AreaLevel: Senior | Advanced Node Experience RequiredRole OverviewYou will own key aspects of the place-and-route (PNR) flow, ensuring design closure across timing, power, and physical verification for complex SoCs at advanced nodes.Key ResponsibilitiesEnd-to-end physical design implementation (floorplan → route → signoff)Timing closure, congestion analysis, and physical optimizationPower planning and IR/EM-aware implementationIntegration with signoff flows (STA, IR/EM, DRC/LVS)Collaboration with RTL, STA, and power integrity teamsFlow improvements and automation using scriptingRequired SkillsStrong experience in PNR for advanced nodes (7nm, 5nm, or below)Expertise with industry tools (Cadence Innovus and/or Synopsys ICC2)Solid understanding of timing closure, signal integrity, and power analysisFamiliarity with EM/IR concepts and signoff flowsScripting skills (Python, Tcl, or Perl)Nice to HaveExperience with multi-die / 2.5D / 3DIC designsExposure to tools like Ansys RedHawk or Cadence VoltusMethodology or flow development experienceWhy Join UsWork on cutting-edge silicon programs where physical design quality directly impacts first-pass success.Interested candidates can apply, refer, or reach out directly: