Hardware Verification Engineer

Job Description for DFT DV Engineer The ideal candidate will work with multi-functional global teams to verify IOBIST and JTAG/IJTAG DFT features on our next generation highly complex server processor products. Work in close collaboration with test engineering team to deliver ATE patterns and post silicon bring-up and debug. The ideal candidate will lead verification of high-performance microprocessors. The candidate is able to work with third party IP. You will develop system level and unit level test plans and test benches for verification of high speed D2D interfaces for UCIe hardware. You will write test benches using System Verilog and UVM. Verify high speed IOBIST interfaces for UCIe test functionality for high performance multi core server class processor. Create test plans for unit-level and chip-level verification. Design and implement test benches and verification environments. Generate test patterns for ATE, debug failures, Yield analysis and evaluate coverage of design. and generate patterns for ATE.Required Skill: 5 to 8 years of Hardware verification experience Have experience building agents, scoreboards and transactors from scratch Good knowledge of high performance microprocessor architecture Understanding of verification methodologyRequired Skills:4 to 6 years of experience Experience in Scan insertion with compression for Stuck-At and At-Speed test. Experience in Scan ATPG (Stuck-At and At-Speed), coverage analysis, simulation and debug Experience in MBIST insertion, simulation and debug on RTL and gates netlist Experience in Boundary Scan insertion, simulation and verification. Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification.(Mentor, Cadence, Synopsys) Good written and verbal communication skills in English STA DFT Test mode timing constraint development and analysis is a plus Knowledge of Verilog HDL and experience with simulators and waveform debugging tools Experience with ATE silicon debug and utilize scripting with perl/Tcl for efficient handling of ATE data a plus.