Memory Layout Engineer (Germany)

Experience:5–7 YearsLocation:GermanyDomain:Semiconductor / Memory DesignRole Overview We are looking for aMemory Layout Engineerwith 5–7 years of hands‑on experience inmemory layout design , specifically onlower technology nodes . The role involves layout development, verification, and close collaboration with design and verification teams.Key ResponsibilitiesPerformmemory layout designfor SRAM / memory blocksWork onlower technology nodes(mandatory)Ensure layout meetsDRC, LVS, and density requirementsOptimize layout forperformance, power, and area (PPA)Collaborate withcircuit design and verification teamsSupporttape‑out activitiesand resolve layout‑related issuesMandatory Skills5–7 years of experience inmemory layout engineeringStrong experience inlower nodes (mandatory)Hands‑on withDRC/LVSclosureGood understanding ofsemiconductor layout fundamentalsGood to HaveExperience with advanced memory architecturesExposure to multiple process nodesStrong communication and teamwork skills#J-18808-Ljbffr