Senior STA Architect for High-Performance Timing Engines

A leading semiconductor firm is seeking an experienced Senior Static Timing Analysis Developer in San Jose, California. This role involves architecting and optimizing timing analysis engines for advanced ASIC and FPGA designs. Candidates should have over 10 years of experience in EDA software development, with deep expertise in STA algorithms and strong C/C++ skills. The position offers the chance to shape next-generation technology and work in a collaborative environment on complex engineering challenges. J-18808-Ljbffr