Senior Network-on-Chip (NoC)

Job Title: Senior Network-on-Chip (NoC) Location : San Jose, California or remote from any US location Duration: Full time Work authorization : US Citizen/US Permanent Resident/H1B/TN Minimum Qualifications MS or PhD in Electrical Engineering, Computer Engineering, or related field. 8+ years of experience in SoC architecture, with 3+ years focused on NoC/Fabric design. Proficiency in Verilog/SystemVerilog with hands-on experience designing and integrating complex SoC subsystems, including bus fabrics and third-party IPs. Strong grasp of computer architecture, interconnect theory, and hardware dataflow. Hands-on understanding of bus protocols (AXI/APD/proprietary) and bus-level SoC integration. Solid knowledge of performance/power tradeoffs and congestion bottlenecks in complex SoC designs. Job Type: Full-time Pay: $250,000.00 - $300,000.00 per year Benefits: 401(k) Dental insurance Health insurance Life insurance Paid time off Vision insurance Education: Master's (Required) Experience: SoC architecture: 8 years (Required) Chiplet: 8 years (Required) Network-on-Chip: 3 years (Required) Verilog/SystemVerilog: 5 years (Required) bus protocols: 5 years (Required) Work Location: Remote