Lead Physical Design Engineer

Company DescriptionTessolve is a leading provider of pre-silicon and post-silicon expertise, delivering efficient turnkey solutions for silicon bring-up and product development. With over 3,500 employees worldwide, Tessolve offers full-service hardware and software capabilities, including advanced silicon and system testing labs. The company specializes in Turnkey ASIC solutions, operating across cutting-edge process nodes and leveraging strong relationships with EDA, IP, and foundries to ensure cost-efficient and risk-mitigated designs. Tessolve also provides end-to-end product design services in the embedded domain with expertise in industries like Avionics, Automotive, Industrial, and Medical. Operating globally with Tier 1 clientele, the company supports innovation with R&D initiatives spanning technologies such as 5G, mmWave, silicon photonics, and more.Lead Physical Design EngineerSan Jose CALongterm Contract Role DescriptionThis is a contract role for a Lead Physical Design Engineer, located on-site in San Jose, CA. The engineer will be responsible for full-chip physical design and verification, including floor planning, power planning, place and route, clock tree synthesis (CTS), and static timing analysis (STA). Key tasks include collaborating with cross-functional teams to analyze and optimize design constraints, resolving timing and design issues, conducting physical verification, and ensuring delivery of high-quality designs that meet performance and power requirements.QualificationsProficiency in Physical Design and Physical Verification, including expertise in floor planning, place and route, CTS, and STA.Experience in Logic Design and understanding of logic optimization and synthesis.Knowledge of Circuit Design principles and methods to ensure reliable and efficient designs.Strong skills in RTL Design to support the entire digital design process.Proficiency with EDA tools TSMC 5nm or 3nm experienceShare resume : amritanshuman.swain@tessolve.com