Physical Design Engineer

Job Role: Physical Design EngineerLocation: Austin, TX or San Jose, CA (Onsite)Employment Type: ContractJob SummaryWe are seeking an experienced Full-Chip Top-Level Physical Design Engineer with strong expertise in chip-level floorplanning, partitioning, power planning, timing constraints, and PPA optimization. The ideal candidate will have hands-on experience with Cadence Innovus and/or Synopsys Fusion Compiler and will work closely with ASIC vendors, IP partners, and block-level physical design teams.Key ResponsibilitiesOwn the full-chip top-level floorplan, including die/partition planning, macro and memory placement, and pin/port alignment across block boundaries.Define partition abutment, repeating structures, channels, and feedthrough strategies for clean block integration.Drive top-level PPA optimization across the chip hierarchy, focusing on power, performance, and area.Plan and review the top-level power grid / PDN in coordination with EM/IR sign-off activities.Develop and maintain top-level SDC constraints and timing budgets.Partition timing constraints and budgets down to individual block owners.Collaborate with ASIC vendors, IP partners, and block-level Physical Design engineers on floorplanning, partitioning, integration, and STA reviews.Identify and resolve top-level physical design issues impacting timing, congestion, power, and area.Participate in design reviews and drive physical implementation closure from top-level planning through sign-off.Required SkillsStrong experience in full-chip / top-level Physical Design.Hands-on expertise in chip-level floorplanning and partitioning.Experience with macro/memory placement and pin/port planning.Strong understanding of PPA optimization, congestion, timing, and power planning.Experience with power grid / PDN planning and EM/IR considerations.Strong knowledge of SDC, timing constraints, timing budgets, and STA.Experience working with block-level PD teams and external ASIC/IP vendors.Hands-on experience with Cadence Innovus.Experience with Synopsys Fusion Compiler is highly preferred.