Mixed Signal RTL Design

About The RoleLead the micro-architecture and RTL design for Mixed-Signal chiplet focused on intelligent power optimization solutions for AI and high-performance computing.What You'll DoArchitect, model, and implement digital PID / cascade control loops (voltage-mode, current-mode, or hybrid) for high-frequency multi-phase IVRs. Develop micro-architecture and implement RTL for control of mixed-signal circuitsTranslate validated MATLAB/Simulink controller models into production-quality RTL (Verilog / SystemVerilog) using HDL Coder or manual high-quality coding. Design and implement supporting digital blocks: ADC interface, DPWM (digital PWM), Perform closed-loop stability analysis on switched power stages. Collaborate closely with analog designers on loop compensation, sensor design, quantization effects, and delay budgeting. Analyze and optimize for area, power, timing, and metastability in the digital controller across PVT corners. Support silicon bring-up, debug, and controller tuning on lab hardware.What We’re Looking ForStrong mixed-signal background: Solid understanding of both analog power circuits (buck converters, 3-level buck, hybrid SC-inductor topologies) and digital control systems, digital filters etc. Expert-level MATLAB / Simulink experience: Proven experience converting MATLAB/Simulink control algorithms into clean, synthesizable RTL (HDL Coder or hand-coded Verilog/SystemVerilog). Deep knowledge of digital PID implementation challenges: quantization, sampling effects, computational delay, fixed-point arithmetic, and limit cycling. Familiarity with high-frequency power converter control and digital PWM modulators (DPWM). Experience with mixed-signal verification flows (analog-digital co-simulation). Good understanding of analog effects impacting digital control: loop delay, sensor non-idealities, inductor non-linearities, PDN resonances. Proficiency in digital design tools: Synopsys VCS, Verdi, Design Compiler, PrimeTime (or equivalent Cadence flow). BSEE / MSEE or PhD with 8+ years of relevant experience in power management ICs or high-performance mixed-signal design. Nice to HavePrior experience designing digital controllers for integrated voltage regulators (IVRs), point-of-load (PoL) converters, or high-current AI/HPC power delivery. Knowledge of advanced topologies: 3-level buck, multi-level converters, hybrid switched-capacitor + inductive converters. Experience with package-integrated magnetics, high-permeability materials, and PDN modeling (Ansys Q3D / SIwave). Experience with formal verification or assertion-based mixed-signal verification. About TylSemi, Inc.The OpportunityThe AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?That's what we solve. TylSemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.This isn't a nice-to-have. It's the critical path.Why NowThe Market WindowThe semiconductor industry is going through its biggest architectural shift in 40 years: Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies. Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually. IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.Culture & Team: How We WorkNo Politics, No BureaucracyThere are no layers, no approval chains, no corporate theater. If you have an idea, we test it. If it works, we ship it. No endless meetings, no PowerPoint presentations to convince middle management.Remote-Friendly, Global Team US team: Bay Area preferred, but we hire the best people regardless of location India team: Building a world-class design center in BangaloreMove Fast, Ship Real ProductsWe're not a research project. We have paying customers, committed capital, and aggressive timelines.This is a company, not a lifestyle business. We're building to win.What We Value Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it. Bias for action. We move fast. Analysis paralysis doesn't fly here. Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware. Low ego, high standards. We don't care about titles or politics. We care about results.The AskIf you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.We're asking you to walk away from that and bet on us.Here's Why You Should The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building. The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo. The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue. The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.This is the bet. Join us and build something that matters.Or stay comfortable. No judgment.But if you're the kind of person who wants to take the shot, we'd love to talk.READY TO JOIN?The Pay Range For This Role Is175,000 - 350,000 USD per year (San Jose (HQ))