Design Verification Engineer

Job Title: Low Power Design & Verification Engineer Primary Skills:UPF/VCLP with Low Power expertise Location: Bay area (onsite) Duration : 12+ Months Job Description : UPF/VCLP with Low Power expertise ng a skilledLow Power Design & Verification Engineerwith strong expertise inUPF (Unified Power Format)andVCLP (VC Low Power) . The ideal candidate will be responsible for defining, implementing, and verifying low-power architectures in complex SoC designs, ensuring compliance with power intent and design specifications. Key Responsibilities Develop and implementpower intent using UPF (IEEE 1801) Define and managepower domains, power states, and supply networks Performlow power verification using VCLP (Synopsys VC LP) Thanks Shaik Sadeq Email: Sadeq@infobahnsw.com