PLL Architect and Design Engineer

PLL Architect and Design Engineer Responsibilities :• Address challenges in advanced node technologies, such as self-heating, electromigration, voltage-controlled oscillator (VCO) linearization and device-level noise optimization• Architect, design and simulate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters) at transistor level using tools like Cadence Virtuoso and Spectre• Be responsible for PLL bring up in the lab, conducting performance characterization using state-of-the-art lab equipment• Conduct comprehensive system-level simulations and validation for PLL integration into advanced transceiver technologies• Supervise and verify layouts produced by layout engineers to ensure floorplanning, matching, and parasitic minimization using advanced node technologies• Understand trade-offs between different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency rangeRequired Skills & Experience :• Master's degree and/or PhD in Electrical Engineering or related fields with 5+ years of relevant experience in PLL design, and production level tape-out experience.• Deep understanding of phase noise analysis, VCO design, LDOs and supporting circuitry associated with PLLs• Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)• Proficient in cadence virtuoso, electromagnetic simulator (e.g., EMX/HFSS), and MATLAB for system-level modelling• Strong communication and documentation skillsJavier LeonTalent AcquisitionChelsea Search Group619-227-3193 cellFJLrecruiter@gmail.com