Lead Engineer FPGA DESIGN
We are looking for candidates more on VHDL and FPGA programming side.
Title: Lead Engineer – FPGA Design
Location: Houston, TX
Duration – Fulltime
Technical Skills
Expert in implementing digital designs in FPGA using VHDL/Verilog
· Should be able to develop and own FPGA designs of reasonable complexity
· Hands-on experience in all FPGA development phases
o RTL coding for synthesis, Testbench development, Functional Simulation, Synthesis, Place and Route, Timing Closure, On board testing
Should have hands on experience in Zynq FPGA SoCs or similar devices
· Should have very good understanding of FPGA internals
· Capability to discuss system level aspects with hardware, software team members
· Good understanding of simple serial communication protocols like IIC, SPI, UART or similar
· Experience in timing closure of designs
· Tool knowledge – Xilinx Vivado or Intel Quartus or ModelSim/QuestaSim or similar EDA tools
Would be a plus:
· Exposure to standard interfaces like AXI-4, AXI-S, Ethernet, PCIe etc.
· · Experience in using Gigabit Transceivers
· · Experience using DDR memory controllers
· · Exposure to lint tools, CDC tools
Job Responsibilities
Understand customer requirements and develop FPGA architecture to meet the requirements
· Identify independent modules in the FPGA architecture and guide engineers to develop detail design of the module and implement them
· Ownership of the top-level FPGA design in projects
· Timing closure of FPGA design
· Mentor at least four engineers
Communication
Good and strong verbal and written communication to involved stakeholders
Preferred qualification
Bachelor of Electronics and Communications Engineering
· Years of Experience : 6 - 9 Years
Job Type: Full-time
Pay: $110,000.00 - $120,000.00 per year
Schedule:
8 hour shift
Ability to commute/relocate:
Houston, TX 77001: Reliably commute or planning to relocate before starting work (Required)
Experience:
FPGA design - Lead engineer: 6 years (Preferred)
candidates more on VHDL and FPGA programming side.: 7 years (Preferred)
Synthesis, Place and Route, Timing Closure, On board testing: 6 years (Preferred)
Work Location: In person