Sr. Staff Test Engineer

About the Role: Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world's most advanced AI and data center infrastructure. We are seeking a Sr. Staff Test Engineer to join our team.As a Sr. Staff Test Engineer, you will serve as a technical leader for test development and manufacturing readiness of Celero's next-generation DSP and mixed-signal SoCs. You will own the end-to-end test strategy-from first silicon to high-volume production-while partnering closely with design, validation, systems, and manufacturing partners.This is a hands-on role with broad technical influence. You will define test architectures, drive methodology, building scalable ATE solutions that ensure product quality and cost efficiency.Key Responsibilities:Technical Ownership:Own test engineering solutions across all product phases: silicon bring-up, characterization, customer sampling, qualification, and high-volume manufacturing.Test Architecture & Strategy:Define test strategy, coverage goals, and manufacturing methodologies; develop comprehensive product Test Plans and drive DFT alignment.ATE Solution Development:Implement all aspects of product test development including:ATE configurationTest software and automationTest hardware including probe cards, load boards, fixturing, and mechanical interfacesCross-Functional Collaboration:Act as a core team member for new product introduction, participating in architecture reviews, testability/DFT reviews to achieve quality and cost requirements.Coverage & Optimization:Partner with Design Engineering to ensure test coverage, yield optimization, and test time targets.Correlation & Characterization:Correlate ATE results with bench validation data; characterize device performance and margins for volume production.Manufacturing Readiness:Coordinate with manufacturing, technology, and sub-con partners to drive NPI test release and volume ramp.Mentorship & Influence:Provide technical guidance and help shape long-term test infrastructure and standards.Required Qualifications:Bachelor's degree in Electrical Engineering or related field with 10+ years of test engineering experience (Master's preferred).Deep expertise with Advantest 93K and/or Teradyne Uflex platforms.Strong background in mixed-signal ATE development for complex SoCs including:High-speed ADC/DACSERDESDSP-based devicesSolid understanding of Scan, MBIST, and loop-back test methodologies.Preferred Qualifications:Familiarity with bench instrumentation such as Network Analyzers and Sampling Oscilloscopes.At-speed wafer probe experience.Experience with schematic capture, PCB layout, and 2D/3D CAD tools.Salary Range$150,000 - $250,000 Annually