Sr ASIC/RTL Design Engineer (NoC / Ethernet / PCIe / UCIe) - Remote

Location: Remote – Anywhere in US / Canada Full-time: Salary + Benefits + Bonuses / Contractor + Stock options Work Status: US citizen or Lawful Permanent Resident. Responsibilities Translate high-level system requirements and customer use cases into detailed architecture and functional specifications. Collaborate with chip and system microarchitects to align ASIC architecture with system-level goals for throughput, latency, and power efficiency. Guide modeling and feasibility analysis of packet flow behavior through the switch datapath to validate architectural choices, including throughput, latency, power and area efficiencies. Work closely with RTL, Verification, Physical Design and Firmware teams to ensure seamless design implementation and handoff. Guide integration of internal and external IPs (e.g. MAC, PCIe, SerDes) into the broader architecture. Drive interface requirements. Participate in design reviews, performance modeling, test and verification strategies and architectural trade-off analysis. Contribute to post-silicon validation for performance and correctness. Investigate and resolve complex issues related to ASIC data path, working closely with cross-functional teams including hardware engineers, firmware developers, and system architects. Qualifications MSEE with 10+ years of experience, preferably in networking ASIC architecture and design. Candidates with experience in related areas of computer and parallel processing architectures – in particular, complex memory crossbars, buffering schemes, scheduling algorithms and high-speed datapaths – are also highly desired. A deep understanding of networking protocols (Ethernet, TCP/IP, UDP, VLAN, MPLS, RoCE, etc.) and their hardware implications, or a willingness to become expert. Demonstrated expertise in microarchitecture definition, performance modeling, and trade‑off analysis. Capability to develop Architecture behavioral models is highly desired. Experience working across the ASIC development lifecycle, from concept through productization. Experience in high‑speed I/O integration (e.g., UCIe, PCIe Gen5/Gen6, SerDes) and Software Control Plane interface architecture is highly desirable. Understanding of physical design implications on packet processing and buffering architecture (e.g., timing, area, power). The anticipated annual base salary for this position is between $170,000 to $210,000, which also includes a comprehensive benefits package. Full-Time Benefits 15 days of PTO per calendar year 10 paid Holidays per calendar year Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents Dental & Vision: Company covers 50% of premiums for Employee and Dependents Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance Employee Assistant Program (EAP) 401k - Traditional & Roth Life/AD&D and Long-Term Disability Tuition reimbursement Equal Opportunity Policy Statement Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances. Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status. #J-18808-Ljbffr