DFT Verification Engineer: RTL & Debug

L&T Technology Services (LTTS) in San Francisco, CA seeks a DFT Verification Engineer with strong RTL and gate-level debugging skills using Verilog/SystemVerilog, simulation, and waveform analysis. The role focuses on pre-silicon and post-silicon verification and debugging of scan and DFT architectures. Responsibilities include integrating Tessent JTAG/SSN, developing verification plans, and building automation to improve efficiency.