dft engineer

DFT EngineerResponsibilitiesDefine & document DFT requirements/Specifications for IP/Block and Chip levelExecute DFT Lint to identify scan DRC violations and resolutionTop level and hard macro block level scan insertion with high EDT compression ratio (Hybrid LBIST, EDT IP/ATPG, LPCT EDT, AC scan verification with high speed PLL, MBIST, and IJTAG)Plan and Insert MBIST and memory repair (BISR) at RTLGenerate and port IJTAG ICL/PDL and STIL patterns for MBIST, ATPG, and JTAG testsATPG pattern verification on pre/post-route gate-level netlist including 0-delay and SDFWork with backend team for the MBIST/Scan mode constraints generation, scan reorder, VCDs for IR drop analysis during DFT, ECO changes and formal verification (LEC), and timing closureSupport test engineer for pattern generation, tester debug and failure analysis.Work with Test Engineering team during Silicon bring-up and creating flow/scripts necessary for debugging/diagnosing compression LPC ATPG patterns (stuck-at/at speed), MBIST patterns on ATE for development and production programsExpert knowledge of Mentor Tessent toolchainJob RequirementsHands-on hierarchical DFT flow experience from RTL to netlistStrong knowledge and experience with both JTAG (IEEE1149.1) and IJTAG (1687)Experience in inserting EDT, wrapper cells and OCCExperience in analyzing DFT DRC violations and fault coverage analysisExpertise in ATPG. Debug and resolve ATPG DRC and chain trace issuesGate level simulations and debug; both 0-delay and with SDF DFTExpertise in using Cadence for scan stitching and Mentor Tessent tool suite for DFT implementationExperience in debugging tester/ATE failures, silicon bring-up and yield and test time improvementExperience in Perl/TCL scripting and good verbal/written communication skills7+ years of proven DFT execution experience on mixed-signal SoC with first-pass silicon success