Lead RTL Design Engineer Energy-Efficient SoC with Equity

Efficient Computer is seeking a Lead RTL Design Engineer to define microarchitecture and implement RTL across the dataflow fabric, memory subsystem, NoC interconnect, and low-power logic. You will work with architects, DV leads, and firmware teams to tape out a power-efficient SoC for edge computing and data centers. You will mentor engineers, drive PPA tradeoffs, and contribute to silicon bring-up while collaborating with compiler teams to optimize hardware execution of graph workloads. #J-18808-Ljbffr