Design Verification Engineer

Key ResponsibilitiesRich experience in constructing highly scalability, configurability, and reusability DV/Performance verification environment.Experience in ASIC design/verification related field in IP, Subsystem or SOC levelExperience in writing System Verilog and/or System C models for simulationWorking experience in writing UVM models, checkers, and stimulus, constructing UVM register models and applying constrained random methodology in UVM test environment and stimulusCompose test plan and validation vectors to ensure functional completenessExperience with design for verification (assertion-based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)Versatile in any one of the high-level verification flows such as SV,UVM, C++ etc. as well as knowledge of industry standard tools for verificationExcellent communication skills (both written and oral)Strong problem-solving skills