Design Verification Engineer

Job Title: Low Power Design & Verification EngineerPrimary Skills: UPF/VCLP with Low Power expertiseLocation: Bay area (onsite)Duration : 12+ MonthsJob Description :UPF/VCLP with Low Power expertiseng a skilled Low Power Design & Verification Engineer with strong expertise in UPF (Unified Power Format) and VCLP (VC Low Power) . The ideal candidate will be responsible for defining, implementing, and verifying low-power architectures in complex SoC designs, ensuring compliance with power intent and design specifications.Key ResponsibilitiesDevelop and implement power intent using UPF (IEEE 1801)Define and manage power domains, power states, and supply networksPerform low power verification using VCLP (Synopsys VC LP)ThanksShaik SadeqEmail: Sadeq@infobahnsw.com