FPGA Verification Engineer with Security Clearance

Job Description Must-Have Skills: UVM (Universal Verification Methodology)SystemVerilogRTL familiarity Key Responsibilities: Develop UVM-based verification environmentsCreate and execute comprehensive verification test plansImplement coverage-driven verification methodologiesCollaborate closely with RTL developers to ensure design quality and functional completenessDevelop automated test frameworks and workflowsDocument verification results, coverage metrics, and testbench performance Requirements: Bachelor's degree in Electrical Engineering, Computer Engineering, or related field7+ years of experience in FPGA verificationExpert knowledge of SystemVerilog and UVMExperience with simulation and verification toolchains (e.g., Questa, VCS, Riviera, etc.)Strong background in testbench development and verification architectureCurrent TS//SCI clearance Desired Skills: Experience with formal verification methodologiesKnowledge of networking protocolsExperience with hardware security verification