Lead ASIC DFT Engineer

Role : Lead ASIC DFT EngineerLocation : San Jose, CA (Remote)Duration : 12 Months Job Description:Experience Required:10+ years of hands-on experience in ASIC Design-for-Test (DFT)Role Summary:We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.Key Skills Required:Strong hands-on ASIC DFT experience with end-to-end ownershipDeep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debugExperience with Synopsys, Cadence, and Siemens/Mentor EDA toolsStrong background in scan insertion, scan chain stitching, ATPG setup, simulation, debug, and DRC analysisMBIST implementation and verification; SMS experience preferredTessent/SSN experience preferredStrong understanding of PLLs, RTL design, synthesis, LEC, and physical design flowsPost-silicon debug and silicon bring-up experienceTCL, PERL, or Python scripting experience is highly preferred