DFT Engineer: Yield & Pattern Debug for AI Data Centers

Broadcom’s Core Switching Group in San Jose, CA is seeking a DFT engineer to advance DFT ATPG, MBIST pattern generation, and yield optimization across the product portfolio. You will debug patterns, support post-silicon activities, and partner with cross-functional teams. The role requires deep CMOS device physics knowledge, experience with DFT tools (Tessent), and strong data analytics. This is a full‑time, on‑site position at our R&D center.