<Back to Search
Senior IC Packaging & SI Architect - Remote
A leading semiconductor technology firm is seeking a Sr Package Design & Electrical Analysis Engineer to drive the physical architecture of high-performance silicon remotely. The role requires over 10 years in package design, focused on ensuring integrity in advanced ASIC designs. Ideal candidates possess strong electrical engineering backgrounds and experience with simulation tools. The position offers a competitive salary between $150,000 and $165,000, along with extensive benefits including medical, dental, PTO, and 401k options.
J-18808-Ljbffr
Showing 100 of 10,785 matching similar jobs in Springbrook, ND
- Engineer - Global Process Packaging
- Applied Scientist, Quantum Device Packaging & Environment R&D, Device Team, AWS Center for Quantum Computing, Device Team
- ASIC Design Verification Engineer I Intern - United States
- (Senior) Principal Engineer (Process and Hardware), Advanced Packaging
- Advanced Optical Component Design and Characterization Researcher
- Director, Heterogenous Integration/Advance Packaging
- VLSI Design Engineer for Server / Data Center Products
- Senior Process Development Engineer
- Package Design Engineer
- Scientist, Integration and Test Engineering
- Senior IC Packaging & SI Architect - Remote
- ASIC/RTL Design Engineer - Senior (US)
- Packaging Engineer
- Manufacturing Design Reliability Engineer
- Applications Development Engineer - FaST
- Section Manager - Microelectronics/Semiconductor Engineering: Device Reliability, Testing, and Analysis
- Quantum Architect (Design)
- Nanofabrication Process Technician, Texas Institute for Electronics
- Electronic and Optical Materials Device Fabrication Engineer
- Applications Development Engineer
- Packaging Engineer
- Senior Low Observables Design & Integration Engineer - Pole Model (Berkeley)
- Equipment Engineer, Plasma Etching and Ion Milling, Microelectronics Research Center
- Test Module Engineer - Advanced Packaging for AI Compute
- Test Engineer
- Senior Package Design Engineer
- Chief Scientist, Photonic Integrated Circuit Process Development - QPIC
- Application Engineer
- Senior Packaging Engineer
- 3D IC Solutions Engineer - Package Design Engineer - EDA
- VLSI Design Engineer - Server/Data Center & AI IPs
- Process Technician
- Scientist, Integration and Test Engineering
- DFT Lead - AI Data Center SoC Architect
- GPU Design Engineer - Memory Hierarchy
- Process Engineer IV - (E4)
- Summer 2026 Process Integration Intern (Bachelor/Masters - Santa Clara, CA)
- Senior Process Engineer - Plasma
- Lead Design Verification Engineer
- Packaging Substrate Engineer