ASIC Physical Design Engineer

We are hiring an experienced ASIC Top‑Level Floorplan Physical Design Engineer to join a high‑impact ASIC team at a leading semiconductor company.In this role, you will work on advanced AI and PCIe switch products and own top‑level physical design from RTL through tapeout.What You Will DoOwn full‑chip floorplanning including die size estimation and partitioningDefine top‑level clock distribution and deliver physical partitionsResolve physical integration challenges related to chip assemblyPartner with package teams on I/O planning, bump mapping, and RDL strategyCollaborate with design and methodology teams across the development cycleDevelop and improve floorplanning methodologies and internal flowsEvaluate internal and third‑party IP from a physical design perspective Required ExperienceBachelor’s degree with 8+ years or Master’s degree with 6+ years of experienceProven experience in top‑level floorplanning and full‑chip physical designStrong background in die sizing, partitioning, clocking, and pin assignmentExperience with large SoCs and complex subsystemsHands‑on experience resolving chip‑level DRC, LVS, and EM or IR issuesSuccessful tapeout experience at advanced process nodes Technical BackgroundExperience with high‑speed and complex IP such as DDR, SerDes, HBM, and PCIeFamiliarity with chiplet or die‑to‑die based designsExperience with bump planning, RDL routing, and multi‑voltage domainsStrong understanding of hierarchical physical design and power grid planningExperience with structured clocking and top‑level placement strategiesProficiency in scripting languages such as Python, Tcl, or Perl What Makes This Role UniqueEnd‑to‑end ownership of top‑level physical designWork on cutting‑edge AI and high‑performance networking siliconExposure to advanced nodes and complex packaging technologiesHigh visibility role with strong cross‑functional influence