Staff Engineer, RTL Memory Centric Computing
Senior Engineer, RTL Memory Centric Computing Location: San Jose, California, United States
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Advancing the World’s Technology Together
Our technology solutions power the tools you use every day—including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.
We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.
The AGI (Artificial General Intelligence) Computing Lab is dedicated to solving the complex system-level challenges posed by the growing demands of future AI/ML workloads. Our team designs, prototypes, and optimizes next-generation AI systems through tight hardware–software co-design, collaborating with hardware and software engineers to address AI/ML workload challenges and explore computing abstractions that balance hardware and software components. We continuously conduct research across memory, computing, interconnect, and AI/ML to ensure our platforms handle demanding workloads, with a focus on affordability and sustainability. Join us in shaping the future of computing.
We are looking for a Senior Engineer, RTL Memory Centric Computing . This role is part of the AGICL lab within DSRA, a research-driven systems lab at the intersection of large language models, accelerator hardware, and high-performance software stacks.
Location : Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.
What You’ll Do
Develop IP for memory centric computing systems using Verilog, System Verilog and HLS
Optimize the IP for performance, power, and area by leveraging advanced design techniques such as pipelining, parallelism, and data compression
Collaborate with Verification engineers to design and develop test plans
Make design decisions out of a large design trade-off space across performance, power, thermal, and cost
Troubleshoot and debug hardware issues and ensure the quality of the design through verification and validation
Stay up-to-date with the latest advancements in machine learning and hardware architecture and contribute to development of new technologies
Communicate effectively with stakeholders, including users, partners, and management, to ensure systems are delivered on time and within budget
Complete other responsibilities as assigned
What You Bring
Bachelor’s with 5+ years, or Master’s with 3+ years, or PhD with 0+ years of industry experience
Strong background in microarchitecture and computer architecture
5+ years of experience in front-end design methodology involving RTL development for complex control and data path IPs
Experience in designing Memory Controller, NOC, Interconnect IP
Experience in Memory Centric computing IP and SOC integration
Experience in AI/ML workloads
Strong analytical and problem-solving skills
Excellent communication and interpersonal skills
Ability to work independently and as part of a team
Inclusive and adaptable to diverse global norms
Avid learner who uses data to build understanding
Collaborative, open to different approaches
Innovative and creative, able to adapt quickly to change
What We Offer
The pay range below is for all roles at this level across all US locations and functions. Individual pay rates depend on factors including function, location, experience, and education. We offer incentive opportunities and a diverse benefits package centered on employee wellbeing, including Medical/Dental/Vision/401k and additional support for employees and their families.
Equal Opportunity Employment Policy
Samsung Semiconductor is an equal opportunity employer. We value a diverse workforce and are committed to providing accommodations throughout recruiting processes for candidates with disabilities or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations.
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