Senior Physical Design Engineer

Senior Physical Design EngineerLocation: Sunnyvale, CAJob Type: Full-timeWork Arrangement: Onsite role, Work from Client Office – 5 days a weekInterview: Two rounds of Video interviewKey ResponsibilitiesDrive RTL synthesis and optimization to achieve performance, power, and area (PPA) goalsPerform floor planning for complex ASIC/SoC designs while ensuring optimal timing, congestion, and power distributionCollaborate closely with RTL design engineers to provide actionable feedback that improves RTL quality, synthesis results, and overall implementationAnalyze netlists and identify opportunities for optimization to improve design quality and implementation efficiencyWork cross-functionally with architecture, RTL, verification, and physical design teams to ensure smooth design convergenceSupport timing closure by identifying implementation bottlenecks and recommending design improvementsParticipate in design reviews and contribute to continuous process and methodology improvementsRequired QualificationsBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related fieldStrong hands-on experience in ASIC/SoC physical design with 10+ years of industry experience.Expertise in RTL synthesis and timing optimizationSolid experience with floor planning for advanced technology nodesStrong understanding of netlist optimization and physical implementation methodologiesExperience collaborating with RTL/design teams to improve design quality and implementation efficiencyExcellent communication and cross-functional collaboration skillsPreferred SkillsExperience with industry-standard EDA tools for synthesis and physical designStrong understanding of timing, congestion, power, and area optimization techniquesExperience working on high-performance CPU, GPU, AI/ML, or networking SoCs is a plus