ASIC Design / Verification Engineer

ASIC Design / ASIC Verification Engineer | AI Silicon StartupLocation: Santa Clara, CA (on-site)Morr0 is hiring for an MIT-founded AI silicon startup hiring across ASIC design and ASIC verification. These are separate opportunities, with scope tailored to your expertise.The company is tackling a major constraint in AI infrastructure: how much memory accelerators can access, and how efficiently data moves between them.Its Memory Processing Unit (MPU) introduces a new memory tier for AI systems, designed to expand accelerator-accessible memory by 1,000x+The ASIC program is led by a 20-year NVIDIA veteran who led early NVLink development. You’ll join an early engineering team with meaningful ownership over the silicon and the decisions behind it.ASIC Design - Work closely with architects and verification engineers to develop the digital logic behind the MPU.Owning microarchitecture and RTL development for individual blocks and subsystems.Designing logic for data movement, memory access, address translation and high-speed connectivity.Translating architectural requirements into designs that balance performance, power and area.Working with verification and implementation teams to debug issues and take designs towards tapeout.ASIC Verification - Help define the verification approach and establish confidence in the design, from individual blocks through full-chip integration.Developing verification plans, environments and testbenches using SystemVerilog and UVM.Building reusable verification components, stimulus, checkers and coverage models.Verifying complex interactions across memory, data movement and interconnect subsystems.Debugging failures alongside designers and driving coverage closure through tapeout.