Design Verification Engineer

Location – Bay Area CA or Austin TX Title – Design Verification Engineer -AIThis is Fulltime/Permanent roleWe need a DV engineer for AMD who has AI experience.The ideal candidate for our AI-based HW IP / SoC development SPW would:Have a good understanding of AI-based HW IP / SoC development.Be on the forefront of general AI trends (e.g., understanding of various LLMs and their relative strengths/weaknesses based on application).Have a baseline understanding of DV, including key measurements (e.g., coverage metrics).Key Responsibilities:Strong understanding of SV and UVM and good debugging skills.Understanding of AMBA protocols.Understand design specs and develop test plans based on functional and architectural requirementsBuild UVM/System Verilog-based verification environments for IP/subsystem/SoC level testingDevelop directed and random testcases, perform coverage analysis, and close functional/code coverageDebug simulation failures and work closely with RTL designers to resolve issuesExecute regression runs, analyze results, and contribute to continuous improvementsIntegrate and run power-aware simulations, low power checks, and work with UPF/CPF as neededCollaborate with DFT/PD/RTL teams and post-silicon validation to ensure design quality across domainsDocument test environments, testplans, and results for internal and external reviews