Senior Chip Verification Engineer

Role DescriptionIn this role, you will help create chip libraries, IP, and complete designs. You will utilize your expertise in DV to ensure quality and functionality throughout our product stack, working alongside a cross-functional team of world-class engineers and researchers.We’re looking for candidates who are passionate about pushing the boundaries of chip design, and excited to work at the intersection of semiconductors and AI.Key ResponsibilitiesCollaborate with ML and SW specialists as one of our verification domain expertsCreate testbenches, test plans, benchmarksDesigning and operating novel automated design verification methodologiesQualificationsBachelor’s or Master’s degrees in EE/CS5-10 years of experience in Design VerificationProficiency in the SystemVerilog and UVM languagesExperience with writing test-plans, test benches, and analyzing coverage metricsExcellent written and verbal communication skillsU.S. Citizen, Permanent Resident, or valid work visaPreferred QualificationsPython coding skills, for EDA automation and design parsing Proficient in the use of Git (branches, pull requests, merging, rebasing …)Knowledge of industry-standard communication protocols (SPI, I2C, AXI, Ethernet, PCIe, DDR5 …)Experience with various verification approaches (SystemVerilog, UVM, CocoTB, Formal Verification …)Experience with FPGA development and/or debug (Vivado, Vitis, Quartus, ACE …)Comfortable working in a dynamic, research-heavy startup environment