Validation Manager

We are looking for Validation Manager @ Santa Clara CAJob description:Title: Senior PCIe/CXL Electrical Validation EngineerLocation: Santa Clara, CA 95054Full time position.Exp level 15-20yrs Basic QualificationsStrong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor’s is required, and a Master’s is preferred.≥5 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for internal meetings in advance, and to work with minimal guidance and supervision.Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!Proven track record solving problems independently, preferably as a tech leadRequired ExperienceFamiliarity with PCIe and CXL specs, especially Electrical Compliance sectionsWorking knowledge of key, high-speed design blocks such as PLL’s, DFE, Tx EQExperience in system testing, characterization, margin analysis and optimization of high-speed PCIe/CXL data links over long and short channelsStrong python scripting ability: knowledge of object-oriented programming and basic dev ops using git for source control and collaborationDeep background in developing bench automation techniques, preferably using Python, with emphasis on execution efficiency, repeatability, and data analysis.Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNAPreferred ExperienceHands-on experience with signal integrity, especially as it relates to PCIe/CXL testing and CEM/NVMe interfacesWorking knowledge of C or C++ for embedded FWFamiliarity with IEEE 802.3x Ethernet standards and both NRZ and PAM-4 signalingWorking knowledge of common serial data specifications such as I2C, SPI, etcKnowledge of schematic capture and PCB layout tools from Cadence, Altium, etc.Knowledge of simulation tools such as MATLAB, Keysight ADS, or PLTS for data analysis and modeling of electrical channel and signal integrity issues