ASIC Physical Design Engineer (TSMC / FinFET)

HiWe’re hiring for a full-time opportunity with a leading semiconductor R&D organization in USA. This role focuses on TSMC advanced node tape-outs (FinFET), customer engagement, and backend sign-off flows. Detailed job description is given below. Title: ASIC Physical Design Engineer (TSMC / FinFET) Location: Lafayette, Indiana (“Relocation assistance provided”)Type: Full time with Client Tapeout, Signoff, DRC/LVS/PEX, Customer interactionJob ResponsibilitiesAct as the primary interface between customers and semiconductor foundries to ensure successful tape-outsGuide customers through design sign-off, including sharing required documentation and technical requirementsCollaborate with internal design, layout, and engineering teams to ensure manufacturabilityPrepare, review, and validate designs for fabrication using EDA toolsSupport customer engagements by providing technical expertise during pre-sales and project executionPartner with customers throughout the chip design and manufacturing lifecycle to ensure a smooth experienceCoordinate with foundry partners (primarily TSMC) on specifications, timelines, and fabrication requirementsTrack project milestones and drive on-time deliveryMaintain accurate documentation of project status, customer communication, and technical detailsIdentify and implement process improvements and automation opportunitiesMust-Have Skills & ExperienceProven tape-out experience with advanced TSMC nodes (e.g., FinFET technologies)Strong understanding of semiconductor backend processesExperience working directly with customers and external partnersExcellent communication skills (written and verbal)Ability to manage multiple priorities and solve complex technical issuesProactive, detail-oriented, and team-oriented mindsetFamiliarity with Linux environmentsBasic scripting or programming experience