DevOps Engineer – Semiconductor EDA Tools & Automation

Overview Join TI to help empower semiconductor design by building secure, scalable DevOps for EDA workloads. You will design and automate pipelines for Cadence PSPICE, Artisan, and related tools across on‑prem and cloud, enabling R&D to innovate faster. Partner with tool vendors and TI EDA teams to deliver reliable, compliant infrastructure using LSF/Slurm and IaC. You will optimize resources and harden security, driving continuous improvement in performance and reliability. Compensation / Benefitscompetitive pay and benefitscountry-specific benefitswell-being support?diversity & inclusioncareer developmentequal opportunity employer ResponsibilitiesDeploy, configure, and automate EDA tools (Cadence PSPICE, Artisan, etc.) in hybrid and cloud environments.Design and manage high‑performance, secure infrastructure for EDA workloads using LSF or Slurm job schedulers.Implement and maintain CI/CD pipelines for EDA application updates, test automation, and environment provisioning.Apply best practices for security, compliance, and operational reliability in semiconductor design environments.Provide technical guidance to engineers and researchers on DevOps, automation, and EDA workload optimization. Key requirementsActive and transferable U.S. government-issued Secret security clearance is highly preferred; must be able to obtain and maintain a Secret security clearanceU.S. citizenshipBachelor’s degree in Computer Science, Engineering, or related field3+ years hands-on experience automating and deploying semiconductor EDA tools (e.g., Cadence Allegro, PSPICE, or Artisan; Altium Designer; AutoCAD; SIMetrix) in enterprise environmentsExcellent communication and collaboration abilityStrong analytical and troubleshooting skillsteam-oriented mindsetDevOps practices and automationinfrastructure-as-code (Terraform, CloudFormation)scripting (Python, Bash)