Performance Modeling Architect - AI Memory Systems

Overview In this role you will develop performance models for a high‑bandwidth AI memory expansion device, collaborating with silicon architects and workload teams. You will explore design tradeoffs, validate performance assumptions, and identify bottlenecks early in development. The work combines hardware and software perspectives to optimize data movement and memory systems at scale. This is an opportunity to shape next‑gen AI memory architectures and influence cross‑functional design decisions. Compensation / Benefitsbase salary plus performance bonus and early‑stage equityhealth, dental, vision, and life insurancerelocation assistance and visa sponsorshipdaily lunch stipend401k matchcollaborative work environment ResponsibilitiesBuild and maintain system‑level performance models for a high‑bandwidth data movement device in a scale‑up contextModel software memory access patterns, data distribution in the network, and on‑device memory channelsCollaborate with silicon architects, system designers, and workload owners to align performance expectationsIdentify bottlenecks, scaling limits, and sensitivity points across compute, memory, and interconnects in end‑to‑end workloadsCommunicate modeling assumptions, limitations, and conclusions to technical and non‑technical stakeholders Key requirementsBachelor or Master degree in Electrical Engineering, Computer Engineering, or a closely related fieldAbility to quickly learn new ML architectures and build performance models for them5–10+ years of experience in performance modeling for data movement devices (NICs, memory expansion cards like CXL, IPU/DPU, NoC)Ability to reason across abstraction layers from architecture to system‑level performancestrong communication skillscollaborative team playerproblem solving with incomplete informationAI memory systemsPerformance modelingMemory expansion devices (NICs, CXL)