CAD Engineer - Timing for Gate-Level Flows u0026 Methodologies

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices!In this role as a member of the STA CAD team, you will be an integral part of the effort to improve the performance of Apple Silicon. You will be responsible for all aspects of static timing methodologies, addressing timing challenges on advanced tech nodes through the development of flows and methodologies used by all Apple Silicon teams in driving timing analysis and closure for first time right silicon.As a member of our STA CAD team, you will:u2028Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designsWork with design teams to understand and debug issues related to constraints, flow scripts, and timing closureFacilitate and drive STA methodology changes to improve overall STA flows as it relates to efficiency/productivity and silicon timing correlationDevelop and maintain scripts and methods for timing analysis and power reductionDevelop and support methodologies, tools, and flows used in the verification of timing constraints, drive best practices across design teamsAnalysis of timing paths to identify key issues, including post-silicon timing debugWork closely with EDA vendors to develop and incorporate new capabilities to solve technical problemsExpert power user of static timing analysis tools and flowsAdvanced programming skills with Python and Tcl or other high level programming languagesProven track record of development and deployment of complex CAD flows and automationFamiliar with STA of large high-performance SoC designs in deep sub-micron technologiesDeep understanding of noise, cross-talk, variation, margins, and timing modelsKnowledge of timing/SDC constraints, hands on experience in creation and validation of constraintsExcellent communicator who can accurately assess and describe issues to management as well as follow solutions through to completionArray