Formal Verification CAD Engineer: Flow & Debug

Apple Inc. is seeking a Formal Verification CAD engineer in Cupertino to design and maintain verification flows for next-generation SoCs. You will develop software for the CAD team and collaborate with internal teams to enable scalable, reliable verification across Apple devices. You will work on property checking, low-power, connectivity checks, SEC, and coverage, while developing CI/CD pipelines and large-scale compute management.#J-18808-Ljbffr