ASIC & FPGA Design Engineer Stf - E4

Overview As FPGA Design Engineer you will shape digital architectures for RF-sensor platforms, turning MATLAB/Simulink models into efficient RTL and integrating onto AMD RFSoC and Versal devices. You’ll collaborate across algorithm, software, and hardware teams to meet radar performance and timing goals. The role combines design, verification, and IP integration with hands-on mentoring of junior engineers. This is a mission-driven opportunity in a high-performance, cross-functional environment. Compensation / BenefitsMedical, Dental, VisionFlexible work arrangements (e.g., 4x10)401(k) matchPaid time off, HolidaysParental LeaveEducation Assistance ResponsibilitiesDefine digital architectures to meet radar/RF-sensor performance and timing goalsConvert MATLAB/Simulink models into synthesizable RTL using Vitis HLS and RTL (VHDL/Verilog/SystemVerilog)Write, simulate, and verify RTL and HLS with self-checking testbenches and functional coverageIntegrate IP blocks and manage clock-domain crossing and timing with Synopsys VCS and Xilinx VivadoPerform place-and-route, timing analysis, and optimization for RFSoC/Versal platformsConduct design reviews, document results, and maintain version controlCollaborate with algorithm, hardware, and software teams for end-to-end integrationMentor junior engineers and foster an inclusive, innovative team cultureSupport system-level validation and board-level testing to verify functional goals Key requirementsB.S. or M.S. in Electrical/Computer Engineering or related fieldProficiency in VHDL, Verilog, or SystemVerilogExperience converting Simulink/MATLAB models into synthesizable code using Vivado HLSExperience with FPGA simulation tools such as Synopsys VCSProficiency with timing analysis, clock-domain crossing, and IP integrationStrong communication and collaboration skillscollaborationmentorshipleadershipVHDL/Verilog/SystemVerilogVivado HLSMATLAB/Simulink