RTL Static Verification Engineer - Tooling & Methodology

AMD in San Jose is looking for an engineer to plan, develop, and maintain EDA tools focused on RTL static checks. The role involves leading the development of a static RTL quality-checking tool, working closely with various teams to integrate the tool into workflows, and supporting design flows. Candidates should have experience with SystemVerilog, scripting languages, and a degree in Electronics or Computer Engineering. Benefits are standard for AMD and equal opportunity is emphasized. #J-18808-Ljbffr