Sr. ASIC RTL Design Engineer

Job Title: Sr. ASIC RTL Design EngineerJob Location: San Jose, CA or Irvine, CACompensation: $150K - $250K base DOE plus equityRequirements: Logic Design, RTL, Processor Architecture, Memory, Cache Subsystems, NoC, InterconnectsPosition OverviewWe are seeking a highly skilled Sr. ASIC RTL Design Engineer to join our innovative team. The ideal candidate will be responsible for designing and implementing complex ASIC designs, focusing on RTL development and ensuring high performance and efficiency in our next-generation products.Key ResponsibilitiesDesign and develop RTL for complex ASIC designsCollaborate with cross-functional teams to define specifications and architecturePerform logic design and data path design for various componentsOptimize designs for performance, area, and power consumptionConduct simulations and validations to ensure design functionalityParticipate in design reviews and provide constructive feedbackSupport the integration of memory and cache subsystems within the architectureWork on interconnect architectures, including NOC solutionsImplement and verify floating-point arithmetic operations in designStay updated with industry trends and advancements in RISC-V architecture.QualificationsBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field5+ years of experience in ASIC design and RTL developmentStrong knowledge of logic design and RTL design methodologiesExperience with processor architecture and system designFamiliarity with memory and cache subsystemsProficiency in interconnect design, including NOCHands-on experience with RISC-V architecture is a plusSolid understanding of floating-point arithmetic and data path design is a plusBenefitsVacation/PTOEquityMedicalDentalVisionLife Insurance401k